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[mkusamy]

I tried to establish addressability for a CSECT from its origin(USING BALRTEST,R12), rather than the current location(USING *,R12). But the program abended with S0C1 when branching to sub program using BALR.

Below code abended with S0C1 at X'12' BALR R14,R15. But the sub program was called without any error when I use USING *,R12.

[RonB]

According to the expansion, the L R15,VSUB becomes 58F0 C068 ( namely Load R15 with the address of Register 12 + an offset of x'68' ). According to the expansion, VSUB is located at offset 68. SO. . .if the content of R12 was ZERO, the L R15,VSUB would load the value of R12 ( Zero ) + an offset of x'68', and all would be well.
However, when you do a BALR R12,0 at offset 4, and then a USING BALRTEST,R12, you set the value of R12 to +4, NOT ZERO. So your L R15,VSUB now translates to loading the value of R12 ( +4 ) + x'68' and you get an invalid address for the following BALR R14,R15.
When you do it the RIGHT way, R12 contains a value of +4 as well, BUT the offsets are then made off of THAT value, not the CSECT start address ( namely, if you look at the expansion you will see that the offset of VSUB will be +64, not +68 ).

Hope that helps.
_________________
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[RonB]

After thinking about what I wrote, I realize that it may sound like I said that the offset of the DC statement for VSUB would show as 000064 instead of 000068. That isn't true. The offset of the DC for VSUB will still show as 000068 - but the expansion of the L R15,VSUB will show 58F0 C064 instead of 58F0 C068.
Also, I didn't mean to imply that there is only ONE "right" way. Any way is "right" code-wise, as long as your USING statement and the address loaded into the Register being USED are in sync. With the "problem" code, you could have said USING BALRTEST+4,R12 and things would have worked OK, since the address in R12 would be the same as BALRTEST+4.
I, myself, normally code such that my Base Register is always aligned with MYCSECT base by loading the Base Register from R15 ( which is supposed to always contain the address of the entry point ), thusly:

[mkusamy]

Thanks.. I got my mistake.
Base register should have been aligned with the CSECT base. I was little careless

Addressability for SAVE also not correct here, but it was not flagged as error because SAVE+4 at offset 6 is actually referring to SAVE+10.